Fault injection in combinational circuits and its power analysis using FPGA

FPGA is used in various current applications like telecommunications, airline traffic control and railway traffic control. So it is essential to evaluate the reliability of the FPGA. It is generally done using the specialized phenomena called as fault injection. The fault injection is done using the instrumented circuit that is being proposed on the paper. Where in the reliability of the combinational circuits are evaluated in terms of computing the delay, power consumption and memory consumption of the corresponding circuit in presence of the faults. In this paper we have taken the array multiplier into account. As the array multiplier logic implies that they are sensitive to memory and enormous power consumption, the alternate architecture is being introduced and the reliability is measured in terms of identifying the three parameters.