ASIC design of reversible full adder circuits

Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nano-computing and optical computing. Reversible logic gates are widely known to be compatible with future computing technologies which virtually dissipate zero heat. Adders are fundamental building blocks in many computational units. For this reason, we have simulated several adder circuits using the reversible gates. This paper implements a design of Adder/Subtractor using reversible logic gates. The first design is an implementation of two´s complement Adder/Subtractor suitable for signed/unsigned numbers. The Full Adder/Subtractor is then applied to design a reversible 4-bit ripple Adder/Subtractor. It has been shown in Cadence´s tools that the reversible circuits outperform the irreversible circuits in terms of delay and power dissipation.