Title :
Hardware implementation of shading models in an application specific integrated circuit
Author :
Ikedo, Tsuneo ; Okuyama, Yuich ; Ma, Jianhua
Author_Institution :
Comput. Archit. Lab., Aizu Univ., Japan
Abstract :
The Truga001 is a single chip rendering processor with 12 embedded graphics functions. Phong and bump mapped shading, reflection and reflection mapping, gaseous object rendering and video mapping are incorporated fully in hardware with a MIMD structure. Shaded and texture mapped pixels are rendered at 3.8 ns/pixel which is equivalent to 1.2 million triangle polygons (100 pixels/s) with hidden surface removal. In the design of the Phong and bump mapped shading circuit, we used angular parameters for defining surface and light source normals instead of vector. This enables the circuit-scale less than 10000 gates/circuit. The chip is fabricated with a 940000 gate standard cell, 0.3 μm CMOS in a TCP/BGA package. The paper describes the hardware architecture and its implementation technologies of the Phong and bump mapped shading in an ASIC
Keywords :
CMOS integrated circuits; application specific integrated circuits; computer graphic equipment; hidden feature removal; microprocessor chips; parallel architectures; rendering (computer graphics); ASIC; CMOS; MIMD structure; TCP/BGA package; Truga001; angular parameters; application specific integrated circuit; bump mapped shading; embedded graphics functions; gaseous object rendering; hardware implementation; hidden surface removal; light source normals; phong shading; reflection mapping; shading models; single chip rendering processor; texture mapped pixels; triangle polygons; video mapping; CMOS technology; Circuits; Graphics; Hardware; Light sources; Optical reflection; Packaging; Paper technology; Rendering (computer graphics); Surface texture;
Conference_Titel :
Shape Modeling and Applications, 1997. Proceedings., 1997 International Conference on
Conference_Location :
Aizu-Wakamatsu
Print_ISBN :
0-8186-7867-4
DOI :
10.1109/SMA.1997.634892