DocumentCode :
2151139
Title :
A new paradigm for trading off yield, area and performance to enhance performance per wafer
Author :
Gao, Yue ; Breuer, Melvin A. ; Wang, Yanzhi
Author_Institution :
Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, USA
fYear :
2013
fDate :
18-22 March 2013
Firstpage :
1753
Lastpage :
1758
Abstract :
In this paper we outline a novel way to 1) predict the revenue associated with a wafer, 2) maximize the projected revenue through unconventional yield enhancement techniques, and 3) produce dice from the same mask that may have different performances and selling prices. Unlike speed binning, such heterogeneity is intentional by design. To achieve these goals we overturn the traditional concepts of redundancy, and present a novel design flow for yield enhancement called “Reduced Redundancy Insertion”, where spares can potentially have less area and performance than their fathers. We develop a model for the revenue associated with the new design methodology that integrates system configuration and leverages yield, area and performance. The primary metric used in this model is termed “Expected Performance per Area”, which is a measure that can be reliably estimated for different system architectures, and can be maximized by using algorithms proposed in this paper. We present theoretical models and case studies that characterize our designs, and experimental results that validate our prediction. We show that using Reduced Redundancy can improve wafer revenue by 10–30%.
Keywords :
Algorithm design and analysis; Kernel; Measurement; Optimization; Pipelines; Rail to rail inputs; Redundancy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Conference_Location :
Grenoble, France
ISSN :
1530-1591
Print_ISBN :
978-1-4673-5071-6
Type :
conf
DOI :
10.7873/DATE.2013.353
Filename :
6513799
Link To Document :
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