Title :
A 5.6-mW power dissipation CMOS frequency synthesizer for L1/L2 dual-band GPS application
Author :
Jia, Hailong ; Ren, Tong ; Lin, Min ; Chen, Fangxiong ; Shi, Yin ; Dai, Foster F.
Author_Institution :
Inst. of Semicond., Chinese Acad. of Sci., Beijing, China
Abstract :
This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver, which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor, the wideband VCO shows a tuning range from 2 to 3.6 GHz to cover 2.45 GHz and 3.14 GHz in case of process corner or temperature variation, with a current consumption varying accordingly from 0.8 mA to 0.4 mA, from a 1.8 V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6 mW working at L1 band with in-band phase noise less than -82 dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1 MHz offset from a 3.142 GHz carrier.
Keywords :
CMOS integrated circuits; Global Positioning System; frequency synthesizers; radio receivers; voltage-controlled oscillators; L1-L2 dual-band GPS application; dual-band GPS receiver; frequency 2 GHz to 3.6 GHz; high Q on-chip inductor; power dissipation CMOS frequency synthesizer; wideband VCO; CMOS process; Dual band; Frequency synthesizers; Global Positioning System; Inductors; Phase noise; Power dissipation; Radio frequency; Tuning; Wideband; CMOS RF; Charge Pump; Frequency Synthesizer; GPS; Low Power; PLL; Phase Noise; VCO;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734864