Low-power hardware implementation of ECC processor suitable for low-cost RFID tags

RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper we propose a novel ALU architecture for ECC processor on tags. By specially restructured the conventional mathematical expressions of Montgomery algorithm, the ALU operation of point multiplication in our design is reduced by nearly 47%. Also, various multipliers, such as bit-serial multiplier, digit-serial multiplier and the divided algorithm are adopted to balance between power consumption and speed. To attain ultra low power consumption, other techniques, such as finite state machines (FSM) optimization, clock gating, pipelining operations and low-power target library are used in the design. The area of the ECC processor is equal to 16.9 k gates equivalents. It performs an elliptic curve point multiplication in 36174 clock cycles and has a power consumption of 6.607 ¿W at 1.28 MHz using TSMC 0.18 ¿m low-voltage cell library.