A low swing differential signaling circuit for on-chip global interconnects

This paper describes a low swing differential signaling scheme for on-chip global interconnects. A simple MOS current mode logic circuit is used to provide an attractive alternative to conventional full swing voltage signaling. The most traditional low swing drivers use additional reference voltages to limit the signal swing. By applying the proposed circuit, a low voltage swing of 110 mV can be obtained which does not need an additional reference voltage. Compared to the conventional full swing circuit, the total energy consumption and energy delay product (EDP) can be reduced by 44.38% and 46.23% respectively, in the simulation of an 1 cm long interconnect wire working under a voltage supply of 1.8 V in SMIC 0.18 ¿m technology.