Title :
A new bandwidth enhancement technique for cascode amplifier
Author :
Somvanshi, Sameer
Author_Institution :
BITS, Pilani, India
Abstract :
In this paper, a new technique is presented to increase the bandwidth for a single stage amplifier. Usually, -3 dB bandwidth of single stage amplifier is in few MHz High output impedance and subsequent capacitive loading decrease the bandwidth of amplifier. The presented technique uses a load which itself acts as bandwidth enhancer. This high speed amplifier is designed on 180 nm CMOS technology, operates at 2.5 V power supply. This amplifier is succeeded by an output buffer to achieve a better linearity, high output swing and required output impedance for matching.
Keywords :
CMOS analogue integrated circuits; amplifiers; CMOS technology; bandwidth enhancement technique; bandwidth enhancer; cascode amplifier; high speed amplifier; single stage amplifier; size 180 nm; voltage 2.5 V; Analog circuits; Bandwidth; CMOS technology; Capacitors; Frequency; High power amplifiers; Impedance matching; Linearity; MOSFET circuits; Power supplies;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734906
