DocumentCode
2152290
Title
A new true-single-phase-clocking (TSPC) BiCMOS dynamic pipelined logic
Author
Tseng, Yuh-Kuang ; Wu, Chung-Yu
Author_Institution
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
49
Abstract
New true-single-phase-clocking BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. The circuit performance of the new BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits are simulated by using HSPICE in 1 μm BiCMOS technology. Simulation results have shown that the operating frequency of the pipelined system which is constructed by the new dynamic latch logic circuits, is 204.1 MHz under 1.5 pF output loading at 2.3 V. It is 2.86 times of the operating frequency in the CMOS TSPC dynamic pipelined system
Keywords
BiCMOS logic circuits; SPICE; flip-flops; pipeline processing; 1 micron; 1.5 pF; 2.3 V; 204.1 MHz; BiCMOS dynamic latch logic circuit; BiCMOS dynamic logic circuit; HSPICE simulation; high-speed pipelined system; true-single-phase-clocking BiCMOS dynamic pipelined logic; BiCMOS integrated circuits; CMOS logic circuits; Circuit simulation; Clocks; Digital audio players; Frequency; Latches; Logic circuits; MOS devices; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706821
Filename
706821
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