Design and implementation of a high-performance 64-bit floating-point reciprocal and square root reciprocal unit

This paper designs a 64-bit floating-point reciprocal and square root reciprocal unit of a stream processor (FT64), which combines the methods of table look-up and functional iteration to implement division and square root operations. This unit which is implemented with two pipeline stages provides the initial value for the iteration of division and square root. A semi-custom and full-custom mixed design method is adopted to improve its performance, and a mixed verification method is also proposed to verify the unit. The results of verification show that the unit can achieve the performance of 1 GHz under the typical condition of 0.13 ¿m CMOS technology.