A dual-ported variable-way L1 D-cache design for high performance embedded DSP

This paper proposes a truly dual-ported variable-way set-associative L1 D-cache design for high performance embedded DSP (Digital Signal Processor). Several power-efficient D-cache optimizations are implemented in the design, which try to reduce the energy consumption of the L1 D-cache without affecting the performance significantly. The strategy to verify the L1 D-cache controller is also presented in this paper, which complements the simulation approach with the formal method by using System Verilog assertions. Experimental results show that miss rate of the L1 D-cache is about 5% better than that of a single-ported one due to dual-ported references. And, the miss penalty is improved by more than 20% compared with a baseline L1 D-cache without these optimizations.