Title :
A compact direct digital frequency synthesizer for system-on-chip
Author :
Xiaodong, Cao ; Weining, Ni ; Ling, Yuan ; Zhikun, Hao ; Yin, Shi
Author_Institution :
Inst. of Semicond., Chinese Acad. of Sci., Beijing, China
Abstract :
A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98% using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter (DAC) has been successfully implemented using standard 0.35 um CMOS process. The core area of the DDFS is 1.6 mm2. It consumes 167 mW at 3.3 V, and its spurious free dynamic range (SFDR) is 61 dB.
Keywords :
CMOS integrated circuits; digital-analogue conversion; direct digital synthesis; read-only storage; system-on-chip; CMOS process; DAC; SoC; compact direct digital frequency synthesizer; data sine mapping; lower power consumption; on-chip digital to analog converter; power 167 mW; quad line approximation technique; quantization and error read only memory technique; sine symmetry technique; sine-phase difference technique; size 0.35 mum; spurious free dynamic range; storage capacity 10 bit; storage capacity 32 bit; system-on-chip; voltage 3.3 V; Adders; Analog-digital conversion; CMOS process; Clocks; Communication switching; Energy consumption; Frequency synthesizers; Quantization; Read only memory; System-on-a-chip;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734921
