Title :
The implementation of 1-GHz bit-stream adder used in signal processing in a 0.18-μm CMOS technology
Author :
Liang, Yong ; Meng, Qiao ; Wang, Zhi-Gong
Author_Institution :
Inst. of RF-&OE-ICs, Southeast Univ., Nanjing, China
Abstract :
A kind of arithmetic and its implementation of bit-stream adder which can be used in digital signal processing were discussed in this paper. Compared with multi-bit adder, the bit-stream adder has the advantages of much simple structure and much small routing area. The ideal circuit model of the bit-stream adder was improved with a pipe line structure to make it work correctly in high frequency range. In order to increase the operating frequency, the physical circuit was deigned with the source coupled logic (SCL) technology. The IC was fabricated with TSMC´s 0.18-μm CMOS process. The chip area is 475 μm ˜570 μm. The experimental results show that the function of the chip matches the demand of design and the chip can work at a frequency of higher than 1 GHz.
Keywords :
CMOS digital integrated circuits; adders; digital signal processing chips; integrated circuit design; CMOS process; bit-stream adder; digital signal processing; ideal circuit model; operating frequency; physical circuit; pipe line structure; source coupled logic technology; Adders; CMOS process; CMOS technology; Circuits; Digital arithmetic; Digital signal processing; Frequency; Routing; Semiconductor device modeling; Signal processing;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734923
