Title :
A CMOS quaternary-to-binary logic decoder
Author_Institution :
Dept. of Electron. Eng., Kangwon Nat. Univ., South Korea
Abstract :
This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 um standard CMOS technology with the supply voltage 2.5 V.
Keywords :
CMOS logic circuits; SPICE; circuit reliability; decoding; multivalued logic circuits; CMOS circuits; HSPICE; current-mode multiple-valued logic; power-delay-product reduction; quaternary-to-binary logic decoder; reliability; voltage 2.5 V; CMOS logic circuits; CMOS technology; Decoding; Integrated circuit interconnections; Inverters; Logic circuits; Logic devices; Signal generators; Very large scale integration; Voltage;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734924
