• DocumentCode
    2152852
  • Title

    A new high compression compressor for large multiplier

  • Author

    Ma, Weinan ; Li, Shuguo

  • Author_Institution
    Inst. of Microelectron., Tsinghua Univ., Beijing, China
  • fYear
    2008
  • fDate
    20-23 Oct. 2008
  • Firstpage
    1877
  • Lastpage
    1880
  • Abstract
    A new high compression compressor is proposed in this paper. This compressor has 7 inputs, 2 output, 2 carry-ins from adjacent two cells and 2 carry-outs to the next two cells. It achieves higher compression ratio than 4:2 compressor, 5:2 compressor and 6:2 compressor. Simulation shows that a 64x64 bit multiplier using this proposed 7:2 compressor is not only 16% faster than multiplier built with 3:2 compressors, but also outperforms multiplier built with other commonly used compressors.
  • Keywords
    adders; carry logic; multiplying circuits; adder; high compression compressor; multiplier; partial product generation; partial product reduction; Circuits; Delay; Microelectronics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-2185-5
  • Electronic_ISBN
    978-1-4244-2186-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2008.4734925
  • Filename
    4734925