DocumentCode
2152868
Title
A framework for automated software partitioning and mapping for distributed multiprocessors
Author
Ramanujan, Ranga S. ; Bonney, Jordan C. ; Thurber, Kenneth J. ; Jha, Rakesh ; Siegel, Howard Jay
Author_Institution
Architecture Technol. Corp., Minneapolis, MN, USA
fYear
1996
fDate
12-14 Jun 1996
Firstpage
138
Lastpage
145
Abstract
One of the major impediments to the widespread use of large-scale, distributed memory multiprocessors is the difficulty of efficiently partitioning and mapping application algorithms onto these machines so as to extract a large portion of the machines´ peak performance. In this paper, we present the preliminary accomplishments of an ongoing effort aimed at automating the complex tasks of software partitioning and mapping during the: system definition phase of application development for distributed memory multiprocessors. We describe a technique called the Augmented Task Dependency Graph (ATDG) for representing the high-level design of the application software. The ATDG allows one to express functional parallelism as well as data parallelism in a manner that facilitates automated partitioning and mapping. We propose a new strategy for searching through the possible space of design choices for partitioning and mapping. The proposed approach, called hierarchical hybrid search, organizes the search space as a hierarchy of sub-spaces. It permits the use of different search techniques for searching through different search sub-spaces. Examples of search techniques that could be employed in the proposed approach include hill-climbing, simulated annealing, and genetic algorithms
Keywords
distributed processing; genetic algorithms; parallel algorithms; search problems; simulated annealing; Augmented Task Dependency Graph; automated software partitioning; distributed memory multiprocessors; distributed multiprocessors; genetic algorithms; hill-climbing; mapping; partitioning; search space; search techniques; simulated annealing; Application software; Computer architecture; Concurrent computing; Distributed computing; Hardware; Impedance; Parallel machines; Parallel processing; Partitioning algorithms; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures, Algorithms, and Networks, 1996. Proceedings., Second International Symposium on
Conference_Location
Beijing
ISSN
1087-4089
Print_ISBN
0-8186-7460-1
Type
conf
DOI
10.1109/ISPAN.1996.508973
Filename
508973
Link To Document