DocumentCode
2152906
Title
Optimization of explicit-pulsed flip-flops for high performance
Author
Zhang, Xiaoyang ; Jia, Song ; Wang, Yuan ; Zhang, Ganggang
Author_Institution
Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Peking, China
fYear
2008
fDate
20-23 Oct. 2008
Firstpage
1885
Lastpage
1888
Abstract
Two novel structures for explicit-pulsed flip-flops are proposed in this paper. The charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. Simulation results also indicate the new structures are ideal for high-speed and low-power digital design.
Keywords
circuit optimisation; circuit simulation; flip-flops; low-power electronics; capacitive load; charging time; discharging time; explicit-pulsed flip-flops; high-speed digital design; interval nodes; low-power digital design; optimisation; short circuit power consumption; Circuit stability; Clocks; Energy consumption; Flip-flops; Latches; Master-slave; Microelectronics; Pulse generation; Sampling methods; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2185-5
Electronic_ISBN
978-1-4244-2186-2
Type
conf
DOI
10.1109/ICSICT.2008.4734927
Filename
4734927
Link To Document