Fully automated physical implementation methodology for Tolapai-the first IA based SoC

The integration of today¿s complex multi-power domain IOs, inherited from legacy ¿Reuse IP¿ sources, poses a big challenge to the full chip physical integration in terms of product cost and design cycle time for products such as Tolapai, the first IA based SoC with IA CPU core, South bridge (ICH), North bridge (MCH), acceleration hardware and networking interfaces. To meet these challenges, the Tolapai design team created the Intel® first fully automated physical implementation methodology that accomplished a 28 percent reduction in the final design convergence cycle from RTL freeze to tape-out with about 20 percent fewer design resources over the entire project. The methodology features a fully automated ASIC implementation method for integrating multi-power well IO blocks, high speed block, and a ¿Correct by Construction¿ solution for the deep sub-micron technology challenges such as strict via density and double via rule on the wide metal without introducing new DRC violations. The automation provides quick turn-around of the several iterations required to achieve performance verification and final convergence while requiring no mask design resources.