Design of 8-bit 250MHz sample-hold circuit

Author

Xiao, Kunguang ; Wang, Yonglu ; Zhou, Shutao ; Yang, Weidong

Author_Institution

Nat. Labs. of Analog ICs, Chongqing, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1953

Lastpage

1956

Abstract

A 0.35 um BiCMOS dual-path, dual-differential sample-and-hold circuit is presented in this paper. The resolution of the circuit reaches 8 bits, and the sampling rate reaches 250 MSPS. The circuit features an alternate working mode, and reduces the circuitÂ¿ demand for speed. From simulation of the circuit, it can be found that SNR is 55.8 dB, that INL and DNL are smaller than that of 8-bit ADC, which is Â±0.2 LSB, and that the power current is 28 mA if the sampling rate is 250 MSPS at an input signal of 1 Vp-p with power supply of 3.3 V. The sample test results are as follows. SNR is 47.6 dB. INL and DNL are lower than that of 8 bit ADC, which is Â±0.8 LSB.

Keywords

BiCMOS analogue integrated circuits; VHF circuits; analogue-digital conversion; sample and hold circuits; ADC; BiCMOS dual-path; analog-digital converter; current 28 mA; dual-differential sample-and-hold circuit; frequency 250 MHz; sample-hold circuit design; size 0.35 mum; voltage 1 V; voltage 3.3 V; working mode; BiCMOS integrated circuits; Circuit simulation; Circuit testing; Data acquisition; Electronic equipment testing; Operational amplifiers; Sampling methods; Signal processing; Signal sampling; Switches; Dual-path; Linearity; SNR; Sample-and-Hold; dual-differential;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734943

Filename

4734943