Title :
A cost-efficient 12-Bit 20Msamples/s pipelined ADC
Author :
Junmin, Cao ; Zhongjian, Chen ; Wengao, Lu ; Baoying, Zhao
Author_Institution :
Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Peking, China
Abstract :
A 12-bit 20 MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5 ¿m CMOS technology, the ADC dissipates 65 mw from a 5 V supply, and achieves a peak SNDR of 70.1 dB with a 1 MHz full-scale sine input at 20 MS/s.
Keywords :
CMOS integrated circuits; analogue-digital conversion; costing; semiconductor optical amplifiers; CMOS technology; SNDR; clock phases; cost efficient; frequency 1 MHz; noise figure 70.1 dB; opamp sharing scheme; passive capacitor error averaging; pipelined ADC; power 65 mW; voltage 5 V; Analog-digital conversion; CMOS technology; Capacitors; Circuits; Clocks; Energy consumption; Microelectronics; Noise reduction; Phase noise; Sampling methods;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734945
