A 2-Bit 4GS/s flash A/D converter in 0.18 μm CMOS for an IR-UWB communication system

A 4 GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC, implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore, because of the low-bit-sampling characteristic of the IR-UWB system, non-time-interleaved structure is used without digital calibration which largely saves the power consumption, chip area and cost. And a differential resistive reference ladder is designed to minimize the inaccuracy of the reference voltage. The proposed ADC dissipates 34 mW power from a 1.8 V supply while operating at 4 GHz. This chip has been fabricated in 0.18 μm 1P6M CMOS process and the ADC achieves 1.86-bit effective number of bits (ENOB) for input signal of 1 GHz at 4 GS/s in simulation of FFT analysis.