Title :
Leakage reduction in differential 10T SRAM cell using Gated VDD control technique
Author :
Singh, Sapna ; Arora, Neha ; Gupta, Neha ; Suthar, Meenakshi
Author_Institution :
FET, Mody Inst. of Technol. & Sci., Sikar, India
Abstract :
In modern era, the demand for memory has been increases tremendously. Due to reduction in SRAM operating voltage, cell stability degradation and the increase in process variation with process scaling. This paper presents a proposed 10T SRAM cell based on a gated-ground nMOS transistor technique and reduces the total leakage power consumption of SRAMs while maintaining their performance. Simulation results with 90nm, 45nm and 32nm process demonstrate that this technique can reduce the total power consumption.
Keywords :
MOSFET; SRAM chips; leakage currents; cell stability degradation; differential 10T SRAM cell; gated-ground nMOS transistor; leakage reduction; process scaling; process variation; size 32 nm; size 45 nm; size 90 nm; total leakage power consumption; CMOS integrated circuits; Capacitance; Logic gates; Random access memory; 10T SRAM; leakage power; power optimization;
Conference_Titel :
Computing, Electronics and Electrical Technologies (ICCEET), 2012 International Conference on
Conference_Location :
Kumaracoil
Print_ISBN :
978-1-4673-0211-1
DOI :
10.1109/ICCEET.2012.6203867
