Leakage reduction in differential 10T SRAM cell using Gated VDD control technique

In modern era, the demand for memory has been increases tremendously. Due to reduction in SRAM operating voltage, cell stability degradation and the increase in process variation with process scaling. This paper presents a proposed 10T SRAM cell based on a gated-ground nMOS transistor technique and reduces the total leakage power consumption of SRAMs while maintaining their performance. Simulation results with 90nm, 45nm and 32nm process demonstrate that this technique can reduce the total power consumption.