DocumentCode
2153393
Title
Low power Folding/Interpolating ADC with a novel dynamic encoder based on ROM theory
Author
Yin, Jilei ; Wang, Yuan ; Jia, Song ; Liu, Zhen
Author_Institution
Inst. of Microelectron., Peking Univ., Beijing, China
fYear
2008
fDate
20-23 Oct. 2008
Firstpage
1969
Lastpage
1972
Abstract
A 6-bit 200 Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35 um digital CMOS process, the whole ADC consumes only 35 mW at a 3.3 V voltage supply.
Keywords
CMOS integrated circuits; analogue-digital conversion; read-only storage; ROM theory; digital CMOS process; digital converter; dynamic encoder; interpolating ADC; low power folding; power 3.5 mW; power dissipation; size 0.35 mum; synchronization logic; voltage 3.3 V; Analog-digital conversion; Binary codes; Logic arrays; Logic circuits; Microelectronics; Power dissipation; Read only memory; Signal generators; Tail; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2185-5
Electronic_ISBN
978-1-4244-2186-2
Type
conf
DOI
10.1109/ICSICT.2008.4734947
Filename
4734947
Link To Document