DocumentCode
2153480
Title
A study of a10-bit 50MS/s low voltage low power pipelined ADC
Author
Zhang, Cuncai ; Wang, Hui ; Cheng, Yuhua
fYear
2008
fDate
20-23 Oct. 2008
Firstpage
1980
Lastpage
1983
Abstract
In this paper, a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in a SMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential solution for low-power high-speed applications, e.g., DVB-H, DVB-T and WLANs.
Keywords
CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; low-power electronics; operational amplifiers; CMOS technology; Nyquist rate ADC; analog-to-digital converter; bootstrapped switch; dynamic comparator; gain-boosted operational amplifiers; power 10.6 mW; size 0.13 mum; voltage 1.2 V; word length 10 bit; Analog-digital conversion; CMOS technology; Circuits; Delay; Digital video broadcasting; Energy consumption; Low voltage; Operational amplifiers; Power supplies; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2185-5
Electronic_ISBN
978-1-4244-2186-2
Type
conf
DOI
10.1109/ICSICT.2008.4734951
Filename
4734951
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