Passivity verification and enforcement of delayed rational function macromodels from networks characterized by tabulated data

Author

Charest, Andrew ; Nakhla, Michel ; Achar, Ram ; Chen, Changzhong

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, ON

fYear

2009

fDate

12-15 May 2009

Firstpage

1

Lastpage

4

Abstract

Passivity has become a critical issue while modeling high-speed networks characterized by tabulated data. For modules containing long delays, macromodeling based on delayed rational functions has been gaining popularity in recent years. However, there are currently no passivity verification or enforcement methods available for such macromodels. To address this issue, this paper proposes passivity verification and enforcement algorithms for delayed rational function macromodels of high-speed modules, characterized by tabulated data. Necessary theoretical foundation and validating examples are presented.

Keywords

high-speed integrated circuits; integrated circuit modelling; delayed rational function macromodels; high-speed networks; passivity verification; tabulated data; Admittance; Analytical models; Circuit simulation; Data mining; Delay; High-speed networks; Signal analysis; Signal design; Transient analysis; Transmission line matrix methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Propagation on Interconnects, 2009. SPI '09. IEEE Workshop on

Conference_Location

Strasbourg

Print_ISBN

978-1-4244-4490-8

Electronic_ISBN

978-1-4244-4489-2

Type

conf

DOI

10.1109/SPI.2009.5089848

Filename

5089848