A novel process technology and cell structure for mega bit EEPROM

Author

Arima, H. ; Ajika, N. ; Morita, H. ; Shibano, T. ; Matsukawa, T.

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

420

Lastpage

423

Abstract

A high-performance CMOS technology and cell structure for a megabit EEPROM are described. A novel EEPROM (electrically erasable programmable read-only memory) cell called a stacked floating gate with self-aligned tunnel region (SSTR) cell has been developed. A merged signal transistor structure has been developed to reduce the cell size. A sufficient cell threshold window is obtained in 2 ms at 16 V in both write and erase operation, using Fowler-Nordheim electron tunneling between the floating gate and the n/sup +/ region. The endurance of the cell is greater than 100000 erase/write cycles. An SSTR cell with a capacitive coupling ratio of 0.83 and a cell area of 30.4 mu m/sup 2/ has been implemented in a 1-Mb EEPROM.<>

Keywords

CMOS integrated circuits; EPROM; integrated circuit technology; integrated memory circuits; 1 Mbit; CMOS technology; EEPROM; Fowler-Nordheim electron tunneling; capacitive coupling ratio; cell area; cell structure; cell threshold window; endurance; merged signal transistor structure; process technology; self-aligned tunnel region; stacked floating gate; CMOS technology; EPROM; Electrons; Nonvolatile memory; PROM; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32845

Filename

32845