• DocumentCode
    2153898
  • Title

    CMOS folding and interpolating ADC with a mixed-averaging distributed T/H circuit

  • Author

    Liu, Zhen ; Jia, Song ; Wang, Yuan ; Ji, Lijiu ; Zhang, Xing

  • Author_Institution
    Inst. of Microelectron., Peking Univ., Beijing, China
  • fYear
    2008
  • fDate
    20-23 Oct. 2008
  • Firstpage
    1921
  • Lastpage
    1924
  • Abstract
    An 8-bit 200 MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2 LSB according to MATLAB simulation results. This ADC is implemented in 0.5 um CMOS technology and the total power dissipation is merely 96 mW at a sampling rate of 200 MHz.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; electronic engineering computing; mathematics computing; CMOS folding and interpolating ADC; MATLAB simulation; analog-to-digital converter; frequency 200 MHz; mixed-averaging distributed circuit; nonlinearity error; power 96 mW; size 0.5 mum; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Clocks; Interpolation; Microelectronics; Power dissipation; Sampling methods; Switches; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-2185-5
  • Electronic_ISBN
    978-1-4244-2186-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2008.4734968
  • Filename
    4734968
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2153898