DocumentCode
2153920
Title
An 8-bit 700Ms/s current-steering DAC
Author
Luo, Lei ; Jun Yan Ren
Author_Institution
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
fYear
2008
fDate
20-23 Oct. 2008
Firstpage
1925
Lastpage
1928
Abstract
This paper is concerned with the design of a high speed current steering DAC. Techniques to improve static precision are preserved while their negative influences on dynamic performance are suppressed. The prototype is implemented with the SMIC 0.13 ¿m process. With an update rate of 700 Msamples/s, measurements show that the DAC achieves over 40 dB SFDR under a sampling rate of 700 Ms/s and consumes 10 mW (8.4 mW for Analog) with 1.2 V voltage supply.
Keywords
digital-analogue conversion; network synthesis; current-steering DAC; dynamic performance; power 10 mW; size 0.13 mum; static precision; voltage 1.2 V; Application specific integrated circuits; Frequency; Impedance; Laboratories; Linearity; Parasitic capacitance; Prototypes; Sampling methods; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2185-5
Electronic_ISBN
978-1-4244-2186-2
Type
conf
DOI
10.1109/ICSICT.2008.4734969
Filename
4734969
Link To Document