Title :
A 10MHz to 600MHz low jitter CMOS PLL for clock multiplication
Author :
Fan, Bing ; Li, Luo-sheng ; Chu, Zi-qiao ; Wang, Dong-Hui ; Hou, Chao-huan
Author_Institution :
Inst. of Acoust., Chinese Acad. of Sci., Beijing, China
Abstract :
This paper describes a phase-locked loop (PLL) designed for clock multiplication. The PLL has a locking range from 10 MHz to 600 MHz at 1.8 V power supply. It has a very low peak-to-peak jitter which less than 50 ps at 150 MHz output frequency. It has been fabricated in a 0.18 ¿m CMOS process. The area of the active layout of the PLL is 560 ¿m * 400 ¿m, and power consumption is about 6 mW.
Keywords :
CMOS integrated circuits; clocks; jitter; phase locked loops; CMOS phase-locked loop; clock multiplication; frequency 10 MHz to 600 MHz; low jitter phase-locked loop; low-power phase-locked loop; peak-to-peak jitter; size 0.18 mum; size 400 mum; size 560 mum; voltage 1.8 V; Charge pumps; Circuits; Clocks; Energy consumption; Filters; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; PLL; VCO; clock jitter;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734970
