Fault tolerant secured system using novel cellular automata

A Cellular Automata based error correcting scheme is used to design a low power, high throughput and hardware efficient system, in which the system requires less number of hardware modules compare than the existing error correcting techniques. In existing Reed-Solomon error correcting and error detecting techniques, there is a possible to correct only a single byte error and detect double byte error, either in check byte or in information byte. By using Cellular Automata (CA) based codes, we can perform simultaneous double byte error correction and double byte error detection in both check byte as well as information byte. And also extended capacity of information bits will be achieved by using Cellular Automata based rules.