A multilevel tungsten interconnect technology

Author

Thomas, D.C. ; Wong, S.S. ; Dinsmore, D.R. ; Soave, R.J.

Author_Institution

Cornell Univ., Ithaca, NY, USA

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

466

Lastpage

469

Abstract

A multilevel tungsten (W) interconnect technology which is inherently planar has been developed to meet metallisation requirements for VLSI. The W interconnect technology relies on implanting Si into oxide channels, which are later selectively filled with W. The technology has been extended to realize three levels of W metallization. Its advantages include a planar surface after each level of metallization, self-aligned and stacked vias, and high resistance to electromigration. The minimum metal pitch is 2 mu m at all levels. Line resistivity is approximately 7 mu Omega -cm, and contact resistance is less than 0.5 Omega /contact.<>

Keywords

VLSI; metallisation; tungsten; 0.5 ohm; 1 micron; 2 micron; 7 muohmcm; VLSI; W interconnect technology; W metallization; contact resistance; inherently planar; multilevel metallisation; oxide channels; planar surface; resistance to electromigration; resistivity; selectively filled with W; self-aligned; stacked vias; three level metal; Conductivity; Current density; Delay; Electromigration; Integrated circuit interconnections; Metallization; Planarization; Space technology; Surface resistance; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32856

Filename

32856