Author_Institution :
Dept. Microelectron., Fudan Univ., Shanghai, China
Abstract :
This paper presents fully digital dedicated on-chip DLLs, allowing for synchronization of external and internal clocks in FPGAs. DLL clock delay compensation circuit, digital clock phase shifter, digital duty-cycle-correction circuit and clock divider. In a Smic 0.18 ¿m CMOS process, its operation frequency range is 25 MHz~300 MHz at 1.8V. The peak-to-peak jitter is 35 ps. Dueing to the digital architecture of the DLL, it only need a single synchronization step when the frequency of the input clock signal is stable. DLL¿s locking time is 13 clock cycles. In addition to providing zero delay with respect to a user source clock, the DLL can provide three phase-shifted version of the source clock. The DLL can also divide the user source clock by up to 16. The values allowed for this property are 1.5, 2, 2.5, 3, 4, 5, 8, or 16; the default value is 2.
Keywords :
CMOS logic circuits; field programmable gate arrays; phase shifters; CMOS process; DLL clock delay compensation circuit; FPGA; clock divider; digital clock phase shifter; digital duty-cycle-correction circuit; digital on-chip DLL; external clock; input clock signal; internal clocks; operation frequency range; peak-to-peak jitter; phase-shifted version; size 0.18 mum; voltage 1.8 V; Clocks; Feedback circuits; Field programmable gate arrays; Frequency conversion; Frequency synchronization; Microelectronics; Phase locked loops; Phase shifters; Propagation delay; Signal generators; Clock delay; Delay-Locked Loop; FPGA; phase shifter;
