Application-dependent interconnect testing of Xilinx FPGAs

This paper presents a novel application-dependent interconnect testing scheme for Xilinx FPGAs. In this scheme, the interconnects in FPGAs´ application configuration (AC) are decomposed into line branches, and the targeted line branches are partitioned into multiple subsets so that the CLBs´ test configurations required to test the line branches in each subset are compatible. Multiple test configurations (TCs) are then generated with one TC for each subset. The experimental results show that this scheme can obtain high stuck-at fault coverage in few TCs.