A new configuration scheme for delay test in non-simple LUT FPGA designs

With the increased use of FPGA in widespread applications, its¿ size and speed has been rapidly increased, so more and more problems associated with performance defects are emerging. Performance defects such as delay defects will not lead to a functional fault, but will limit the frequency of the system. Only Stuck-at testing has not been sufficient to guarantee the reliability and quality, so testing delay fault becomes necessary. In this paper, in order to improve the efficiency and coverage of delay test, we first select the most suitable delay fault model for FPGAs, which is a good simulation for the actual situation. At the same time we proposed a new configuration on the basis of this. This method takes full advantage of the FPGAs¿ reconfiguration feature. It not only omits complex test pattern generation, but also optimizes the BIST circuits to minimize the area cost, and reaches higher fault coverage. To verify the theory, we use Xilinx vertex4 devices on the experimental test, and achieved approving results.