A novel FPGA manufacture-oriented interconnect fault test

Author

Zhao, Jianbing ; Feng, Jianhua ; Lin, Teng ; Tong, Zhiwei

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

2091

Lastpage

2094

Abstract

This paper presents a novel build-in-self-test (BIST) manufacture-oriented interconnect test strategy of SRAM-based field programmable gate arrays (FPGA). Programmable switches (PSs) and line segments are tested separately, which is different from previous methods. An improved depth-first-search (DFS) algorithm is developed for automatically deriving minimal or near minimal test configuration patterns for switch matrix (SM) test. Switch stuck-off, stuck-on faults and line open, short and bridging faults are covered. The experiment on Xilinx vertex FPGA validates the new strategy.

Keywords

SRAM chips; built-in self test; fault diagnosis; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; switches; tree searching; FPGA; SRAM; bridging faults; build-in-self-test; depth-first-search algorithm; field programmable gate arrays; line open faults; line segments; manufacture-oriented interconnect fault test; programmable switches; short faults; stuck-off faults; stuck-on faults; switch matrix test; Automatic testing; Built-in self-test; Fault detection; Field programmable gate arrays; Logic arrays; Logic testing; Multiplexing; Pulp manufacturing; Samarium; Switches; BIST; DFS; FPGA interconnect test;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734989

Filename

4734989