Title :
The affect of cache to speedup models
Author :
Yibo, Xue ; Lan, Chen ; Chengde, Han
Author_Institution :
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Abstract :
Speedup is usually used to reflect the effect of parallel processing systems. But the existing speedup models do not consider the effect of cache, so the effect of cache on several speedup models is analysed in this paper
Keywords :
cache storage; parallel architectures; performance evaluation; cache; parallel processing; speedup; speedup models; Algorithm design and analysis; Computer performance; Concurrent computing; Costs; High performance computing; Parallel processing; Sun; Tin;
Conference_Titel :
Parallel Architectures, Algorithms, and Networks, 1996. Proceedings., Second International Symposium on
Conference_Location :
Beijing
Print_ISBN :
0-8186-7460-1
DOI :
10.1109/ISPAN.1996.508991
