Design and analysis of Carry Bypass Adder using CNTFET

This paper enumerates the efficient design and analysis of a Carry Bypass Adder using Full Adder cell. The Full Adder is designed using Stanford University CNTFET model and proposed 10nm CNTFET model. There are many issues facing while integrating more number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems, the carbon nano tubes have promising applications in the field of electronics. The carbon nanotube is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage at 0.9V. Simulations and analyses are carried out for the Full Adder Cell and Carry Bypass Adder. The simulation results are presented and the analyses are compared with circuits designed using 32nm MOSFET. The comparison of results indicated that the proposed 10nm CNTFET based design is more efficient in power savings and speed.