Design and implementation of a high speed parallel architecture for ATM UNI

Author

Tseng, Wen-Yu ; Chen, Chin-Chou ; Wei, David S L ; Kuo, Sy-Yen

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1996

fDate

12-14 Jun 1996

Firstpage

288

Lastpage

294

Abstract

In this paper, a parallel architecture is proposed to support the operations described in the ITU-T Recommendation I.432 (B-ISDN user-network interface-Physical layer specification). It is rather difficult to perform their operations on a bit serial architecture at a high rate. This paper demonstrates how these tasks can be achieved by means of parallelism. First, we describe the user-network interfaces in general and their physical layer properties. Then a parallel architecture is proposed with a general translation method which converts the serial operation into the parallel one. The application of the parallel architecture on each function is also depicted and the system has been realized in hardware using CMOS technology

Keywords

B-ISDN; asynchronous transfer mode; network interfaces; parallel architectures; ATM UNI; B-ISDN user-network interface; high speed parallel architecture; parallelism; physical layer properties; user-network interfaces; Asynchronous transfer mode; B-ISDN; Bit rate; CMOS technology; Computer science; Design engineering; Frequency; Network interfaces; Parallel architectures; Physical layer;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Architectures, Algorithms, and Networks, 1996. Proceedings., Second International Symposium on

Conference_Location

Beijing

ISSN

1087-4089

Print_ISBN

0-8186-7460-1

Type

conf

DOI

10.1109/ISPAN.1996.508995

Filename

508995