Title :
A 0.25 μm CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range
Author :
Sutoh, Hiroki ; Yamakoshi, Kimihiro ; Ino, Masayuki
Author_Institution :
NTT Syst. Electron. Lab., Kanagawa, Japan
Abstract :
This paper describes a wide frequency range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 μm CMOS/SIMOX technology. This generator supports internal clock frequency to external clock frequency ratios of 2,4,8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 400 MHz. At 400 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW
Keywords :
CMOS integrated circuits; SIMOX; clocks; jitter; large scale integration; phase locked loops; pulse generators; voltage-controlled oscillators; 0.25 micron; 14 mW; 2 V; 5 to 400 MHz; 50 ps; CMOS/SIMOX circuits; PLL clock generator; gate array LSI; internal clock frequency/external clock frequency ratios; lock range; operating frequency range; peak-to-peak jitter; power dissipation; supply voltage; voltage-controlled oscillators; CMOS technology; Clocks; Frequency; Jitter; Large scale integration; Phase locked loops; Phased arrays; Power dissipation; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606581
