Effect of N-type CNTFET on Double edge triggered D flip-flop based PISO shift register

This paper enumerates the efficient design and analysis of Parallel in serial out (PISO) shift register using N-type CNTFET Double Edge Triggered D Flip-flop. The Flip flop is designed using Ballistic CNTFET (VHDL-AMS model) with the dcnt of Inm in resistive load inverter logic. The transient and power analysis are obtained with operating voltage at 0.6V for the Double edge triggered D flip-flop and PISO shift register using system vision tool. There are many issues facing while integrating many number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by Considering the carbon nano tube have promising application in the field of electronics. The simulation results are presented, and the power consumptions are compared with the conventional MOSFET design. The comparison of results indicated that the CNTFET based design is capable of efficient power savings.