Low power and high performance Zipper domino circuits with charge recycle path

A charge recycle technique is proposed in this paper to lower the dynamic power and to improve the performance of the Zipper domino circuits. Zipper domino circuits of different structures are designed utilizing this technique and simulated based on 65 nm, 45 nm and 32 nm BSIM4 SPICE models. The simulation results show that the power-delay product (PDP) is reduced by up to 42.37% as compared to standard domino circuits. What¿s more, a power distribution method is introduced in Zipper CMOS full-adder design. Through this method, the charge recycle path is optimized to minimize the power.