Noise tolerant circuit techniques for high performance feedthrough logic

Feedthrough logic (FTL) improves the performance of arithmetic circuits as compared to static and dynamic logic. This paper presents a circuit design technique to improve noise tolerant of FTL. However the noise tolerant of feedthrough logic is less as compared to static CMOS circuits. The ANTE (average noise threshold energy) metric is used for the comparison of noise tolerance of proposed circuit with the existing FTL logic. A 2-input NAND gate is designed by the proposed technique. Simulation results for a 2-input NAND gate using 0.18 μm. 1.8 V CMOS process technology shows that the proposed noise tolerant circuit achieves 2.3X ANTE improvement along with the reduction in leakage power and at 90nm the ANTE is improved by 2.1X.