Title :
Low power design and implementation for a SoC
Author :
Yu Zhi-guo ; Wei Jing-he
Author_Institution :
58th Res. Inst., CETC, Wuxi, China
Abstract :
A set of SoC low power design methods is presented based system level, IP module level and gate level. These methods were applied to low power design of a SoC. The SoC power simulation results showed that the static and dynamic power of this SoC was quite low. The goals of the low power design methods applied on the design were achieved. The SoC has been implemented in 0.18 ¿m COMS process, the area is 8 × 8 mm2, the operation frequency is 80 MHz and the power dissipation is about 454.268 mW.
Keywords :
CMOS logic circuits; field effect MIMIC; integrated circuit design; logic design; low-power electronics; system-on-chip; COMS process; IP module level design; frequency 80 MHz; gate level design; low-power SoC design; power 454.268 mW; power dissipation; size 0.18 mum; system level design; Capacitance; Clocks; Design methodology; Energy consumption; Energy management; Equations; Frequency conversion; Oscillators; Power dissipation; Switching circuits;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4735003
