ESD protection for submicron CMOS circuits-issues and solutions

Key issues pertinent to design with advanced CMOS ESD (electrostatic discharge)-protection circuits are discussed. Input protection elements and their limitations with respect to output and power supply applications are examined. The lateral silicon-controlled rectifier has proved to be an effective primary protection element for a wide range of CMOS processes when it is combined with an optimized secondary protection network. Significant features of the dual-diode-output protection circuit as well as special layout considerations for the n-channel device are introduced. Power supply protections has been achieved on advanced CMOS devices by utilization of a standard guard ring configuration which ensures that parasitic silicon-controlled rectifier devices within the internal circuit have the same switching level and that switching is accomplished before BV/sub ceo/ is developed across the parasitic npn device.<>