Heterogeneous multi-core SOC architecture for MPEG decoding

To deal with nowaday multi-standard audio and video processing, a heterogeneous multi-core SOC architecture is presented in this paper, which is composed of a general purpose RISC processor, an audio processing enhanced DSP and dedicated video processing accelerators. To exploit the task level concurrency among audio-video media decoding, an efficiency and flexible HW/SW cooperating architecture is provided for video decoding, a DSP core is integrated for audio decoding individually, and special mechanisms are designed for inner cores communication and data exchange. The proposed architecture is proto-typed on a FPGA system, which can achieve the MPEG-1/2/4 ASP audio-video real-time decoding in the case of 33 MHz system frequency.