A buried-trench DRAM cell using a self-aligned epitaxy over trench technology

Author

Lu, N.C.C. ; Rajeevakumar, T.V. ; Bronner, G.B. ; Ginsberg, B. ; Machesney, B.J. ; Sprogis, E.J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

588

Lastpage

591

Abstract

A novel three-dimensional buried trench (BT) memory cell, suitable for DRAM (dynamic random access memories) of 64 Mb or beyond, has been demonstrated. It uses a novel self-aligned-epitaxy-over-trench (SEOT) technology which allows the fabrication of the cell horizontal access transistor in bulk material epitaxially grown over the trench capacitor. The via connection between the access transistor and the buried trench is a vertical sublithographic contact self-aligned to the trench. This BT cell, with a minimum of 10.8 lithographic squares, was fabricated in a submicron n-well epitaxial CMOS process incorporating the SEOT technology.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; semiconductor epitaxial layers; 3D buried trench memory cell; 64 Mbit; SEOT; ULSI; buried-trench DRAM cell; dynamic random access memories; self-aligned-epitaxy-over-trench; submicron n-well epitaxial CMOS process; trench capacitor; vertical sublithographic contact self-aligned; via connection; CMOS process; CMOS technology; Capacitors; Epitaxial growth; Epitaxial layers; Fabrication; Lithography; Neck; Random access memory; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32883

Filename

32883