DocumentCode :
2154876
Title :
The implementation methods of high speed FIR filter on FPGA
Author :
Li, Ying ; Peng, Chungan ; Yu, Dunshan ; Zhang, Xing
Author_Institution :
Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Peking, China
fYear :
2008
fDate :
20-23 Oct. 2008
Firstpage :
2216
Lastpage :
2219
Abstract :
This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.
Keywords :
FIR filters; distributed arithmetic; field programmable gate arrays; FPGA; Xilinx CoregenTM; Xilinx Spartan 3; add-and-shift method; advanced calculation schedule; field programmable gate arrays; full custom distributed arithmetic; parallel multiplication implementation; sixteen-order high-speed finite impose response filter; Arithmetic; Circuit synthesis; Digital signal processing; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Job shop scheduling; Microelectronics; Programmable logic arrays; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
Type :
conf
DOI :
10.1109/ICSICT.2008.4735011
Filename :
4735011
Link To Document :
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