• DocumentCode
    2154931
  • Title

    An 8-Bit 4-GS/s 120-mW CMOS ADC

  • Author

    Hegong Wei ; Peng Zhang ; Datta Sahoo, Bibhu ; Razavi, Behzad

  • Author_Institution
    Univ. of California, Los Angeles, Los Angeles, CA, USA
  • fYear
    2013
  • fDate
    22-25 Sept. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A four-channel time-interleaved pipelined ADC employs a new timing calibration technique to suppress mismatch-induced spurs and achieve a Nyquist-rate SNDR of 44.4 dB. Designed in 65-nm CMOS technology, the ADC draws 120 mW, providing an FOM of 219 fJ per conversion step.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; calibration; logic design; CMOS ADC; CMOS technology; Nyquist-rate SNDR; energy 219 fJ; four-channel time-interleaved pipelined ADC; mismatch-induced spurs; power 120 mW; size 65 nm; timing calibration technique; word length 8 bit; CMOS integrated circuits; CMOS technology; Calibration; Clocks; Logic gates; Semiconductor device measurement; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2013 IEEE
  • Conference_Location
    San Jose, CA
  • Type

    conf

  • DOI
    10.1109/CICC.2013.6658420
  • Filename
    6658420
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2154931