A reconfigurable power efficient correlator for channel estimation in DTMB system

This paper presents a power efficient reconfigurable correlator for DTMB channel estimation. In this design, a novel architecture based on fast Walsh transform is adopted to perform cyclic correlation. By sharing memory and reusing calculation unit, the proposed reconfigurable architecture supports correlation of PN sequence with code length of 256 and 512 without any increment in hardware cost. Based on SMIC 0.18 ¿m standard CMOS technology, the circuit area of presented design is about 41355 gates. The simulation results show that the proposed correlator saves 60% power consumption compared with those of the existed architectures.