DocumentCode
2154980
Title
A method to lower power in speed negotiation algorithm of fiber channel
Author
Jin, Jie ; Dun Shan ; Cui, Xiao Xin
Author_Institution
Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China
fYear
2008
fDate
20-23 Oct. 2008
Firstpage
2132
Lastpage
2135
Abstract
In this paper, we propose a simple but effective method to reduce the power in the design of the speed negotiation algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area.
Keywords
storage area networks; transport protocols; clock-gating methodology; fiber channel; partition algorithm; power consumption; speed negotiation algorithm; storage area network; transmission protocol; Algorithm design and analysis; Analytical models; Automata; CMOS technology; Clocks; Laboratories; Microelectronics; Optical fiber devices; Partitioning algorithms; Storage area networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2185-5
Electronic_ISBN
978-1-4244-2186-2
Type
conf
DOI
10.1109/ICSICT.2008.4735017
Filename
4735017
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